1. Field of the Invention
The present invention relates to an image display device and an image display panel wherein a so-called point sequential clock driving system is applied to a drive circuit.
2. Description of the Related Art
FIG. 1 and FIG. 2 are block diagrams of configuration examples of image display panels wherein the point sequential clock driving system is applied.
Image display panels 1A and 1B comprises, as show in FIG. 1 and FIG. 2, a pixel portion 2 arranged with pixels in a matrix, a vertical drive circuit (V.DRV) 3, a horizontal drive circuit (H.DRV) 4 and a precharge circuit (P.CHG) 5 as various circuits connected to the pixel portion 2.
The pixel portion 2 uses, for example, a liquid crystal cell as a display element (pixel) of an image. Each liquid crystal cell is provided with a liquid crystal element and a Thin Film Transistor (TFT) that is turned on when displaying for supplying a video signal SP to one electrode (pixel electrode) of the liquid crystal element. While not particularly shown, gates of the TFT on each row (one display line) are connected to a gate line and either one of the sources and drains of the TFT on each column are connected to a data line. The vertical drive circuit (V.DRV) 3 scans (sequentially drives every predetermined time) gate lines when displaying an image, and the horizontal drive circuit (H.DRV) 4 point-sequentially supplies display data of an amount of one display line to the data line (horizontal scan) in a driving time of the gate line (horizontal scan period). By combining the horizontal scan and the vertical scan, an image of one screen is displayed on the pixel portion 2.
In the point sequential clock driving system, the horizontal drive is controlled by a horizontal clock.
In the configuration example shown in FIG. 1, a clock generation portion 6 inside the panel generates horizontal clocks (hereinafter, referred to as drive clocks) DCK1 and DCK2 having a pulse width of a smaller duty ratio and reversed phases to each other and their inverted drive clocks DCK1X and DCK2X based on horizontal clocks HCK and HCKX having reversed phases to each other input from outside. When the horizontal drive circuit (H.DRV) 4 receives a horizontal start pulse (HST: not shown) from the outside or the clock generation portion 6, it shifts the horizontal start pulse (HST) by a built-in shift register driven by input horizontal clocks HCK and HCKX having reversed phases to each other, extracts drive clocks DCK1 and DCK2 based on the shifted pulse and generates a drive pulse for driving a data sampling switch (HSW). The data sampling switch (HSW), while not particularly illustrated, is provided to an output stage of the horizontal drive circuit (H.DRV) 4 or a video signal input portion of the pixel portion 2 and samples point-sequentially an input video signal by the horizontal drive pulse. Note that, in FIG. 1, a clock buffer circuit 7 is provided in accordance with need. In this case, the clock buffer circuit 7 adjusts the horizontal clock HCK by using the horizontal clock HCKX, adjusts the drive clock DCK1 by using the drive clock DCK1X, adjusts the drive clock DCK2 by using the drive clock DCK2X and outputs the adjusted drive clocks DCK1 and DCK2. Also, the clock buffer circuit 7 converts a voltage level of various clocks to a voltage suitable to panel driving.
On the other hand, in the configuration example shown in FIG. 2, the horizontal clock HCK and its inverted clock HCKX, drive clocks DCK1 and DCK2 and their inverted drive clocks DCK1X and DCK2X for driving the horizontal drive circuit (H.DRV) 4 are all given from outside of the panel.
Note that a start pulse and a clock for driving the vertical drive circuit (V.DRV) 3 are omitted in FIG. 2. Also, in this case, a clock buffer circuit 7 having the same function as that in FIG. 1 is provided in accordance with need.
An active element of the variety of circuits incorporated in the panel is composed of a large number of TFTs formed on the same substrate as that of the pixel portion 2. The TFT has larger characteristic variation compared with a bulk transistor, and the characteristic is easily changed by aging and other heat treatment. When the characteristic of the TFT changes, particularly, a sample timing by the data sampling switch (HSW) is deviated. The deviation of the sample timing causes a phenomenon called “ghost”, that is, an undesirable image generated by deviating by certain dots from a correct image position overlaps with the correct image on the display screen.
To prevent the ghost, there is known a timing adjustment technique of sampling an operation by detecting deviation of the sampling pulse due to changes of characteristics of the transistor and feeding it back to the generation of timing of the horizontal clock.
FIG. 9 is a view of a configuration example of a detection circuit provided inside the horizontal drive circuit 4.
The detection circuit 100 of the present example deals with the fact that the data sampling switch HSW for actually sending a video signal to pixels is composed of a high speed CMOS transfer gate. Namely, the detection circuit 100 comprises a CMOS transfer gate 101 provided at a position adjacent to the data sampling switch HSW for sending a video signal to pixels in the horizontal drive circuit 4, and the transfer gate 101 is composed of a TFT to be formed at a time having the same size as that of the CMOS transfer gate composing the data sampling switch HSW.
The CMOS transfer gate 101 comprises a PMOS transistor 101P and a NMOS transistor 101N wherein sources are connected to each other and drains are connected to each other. The mutually connected one terminal is grounded here, while it is connected to a supply line of a video signal SP in the data sampling switch HSW.
Based on a drive clock DCK1 (or DCK2) to be input, a circuit 102 for generating a pair of horizontal drive pulses DP and DPx having reversed phases to each other is connected to gates of the two transistors 101P and 101N.
The mutually connected other terminal is taken out to the outside of the panel via wiring and connected to an input of a so-called feedback IC 110. A node in the middle of the wiring is connected to a supply line of a power source voltage Vdd via a pull-up resistance 111.
When the CMOS transfer gate 101 turns on in the case horizontal drive pulses DP and DPx are applied, a potential of the output shifts from a state of being pulled up by the power source voltage Vdd to the ground potential GND. When the application of pulses is finished, the CMOS transfer gate 101 turns off, so that a potential of wiring rises in accordance with at time constant determined by resistance RL and a capacitance CR of the wiring.
The feedback IC 110 detects the potential change from a high level to a low level and detects the deviation of a phase of the horizontal drive pulse from a potential change amount. More specifically, the output of the CMOS transfer gate 101 changes to the maximum (or a constant value close to the maximum) when there is no phase deviation, while when there is a phase deviation, the potential change amount becomes small in accordance with the deviation amount. The feedback IC 110 estimates the deviation amount of the phase from the potential change amount, adjusts the timing of generating pulses of the horizontal clocks HCK and HCKX so as not to cause phase deviation, and sends it back to the image display panel again.
However, there is a case where particularly the low level of a detection signal is not lowered completely to the ground potential GND, due to deterioration of characteristics of the TFT. In this case, the potential at the low level varies in accordance with how the characteristics of the TFT decline and does not become constant. The feedback IC 110 basically estimates the deviation amount of a phase by using as a reference the potential difference of the power source voltage Vdd and the ground potential GND (or a constant value close to that), but the reference fluctuates in this case. As a result, the accuracy of feedback control declines and the timing of the clock is adjusted to a wrong value.
The decline of accuracy of feedback control becomes notable as the number of horizontal pixels of the image display panel increases and the cycle of the sampling pulse becomes shorter.
Also, when off-leakage of the TFT increases due to the characteristic decline, a current flows from the power source voltage Vdd to the ground potential via the CMOS transfer gate 101 in a turned off state, and consequently, power consumption increases in the image display device or image display panel.